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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GITS_CTLR, ITS Control Register</h1><p>The GITS_CTLR characteristics are:</p><h2>Purpose</h2>
        <p>Controls the operation of an ITS.</p>
      <h2>Configuration</h2>
        <p>The ITS_Number (bits [7:4]) and bit [1] fields apply only in FEAT_GICv4 implementations, and are <span class="arm-defined-word">RES0</span> in FEAT_GICv3 implementations.</p>
      <h2>Attributes</h2>
        <p>GITS_CTLR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">Quiescent</a></td><td class="lr" colspan="22"><a href="#fieldset_0-30_9">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">UMSIirq</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">ITS_Number</a></td><td class="lr" colspan="2"><a href="#fieldset_0-3_2">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">ImDe</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">Enabled</a></td></tr></tbody></table><h4 id="fieldset_0-31_31">Quiescent, bit [31]</h4><div class="field">
      <p>Read-only. Indicates completion of all ITS operations when GITS_CTLR.Enabled == 0.</p>
    <table class="valuetable"><tr><th>Quiescent</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The ITS is not quiescent and cannot be powered down.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The ITS is quiescent and can be powered down.</p>
        </td></tr></table><p>For the ITS to be considered inactive, there must be no transactions in progress. In addition, all operations required to ensure that mapping data is consistent with external memory must be complete.</p>
<div class="note"><span class="note-header">Note</span><p>In distributed GIC implementations, this bit is set to 1 only after the ITS forwards any operations that have not yet been completed to the Redistributors and receives confirmation that all such operations have reached the appropriate Redistributor.</p></div><p>In FEAT_GICv3, FEAT_GICv3p1, and FEAT_GICv4, when GITS_CTLR.Enabled == 1, the value of GITS_CTLR.Quiescent is <span class="arm-defined-word">UNKNOWN</span>.</p>
<p>In FEAT_GICv4p1, when GITS_CTLR.Enabled == 1, the value of GITS_CTLR.Quiescent reads as 1 until the write to Enabled has taken effect and then reads as 0.</p><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to <span class="binarynumber">1</span>.
</li></ul></div><h4 id="fieldset_0-30_9">Bits [30:9]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-8_8">UMSIirq, bit [8]</h4><div class="field">
      <p>Unmapped MSI reporting interrupt enable.</p>
    <table class="valuetable"><tr><th>UMSIirq</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The ITS does not assert an interrupt signal when <a href="ext-gits_statusr.html">GITS_STATUSR</a>.UMSI is 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The ITS asserts an interrupt signal when <a href="ext-gits_statusr.html">GITS_STATUSR</a>.UMSI is 1.</p>
        </td></tr></table>
      <p>If <a href="ext-gits_typer.html">GITS_TYPER</a>.UMSIirq is 0, this field is <span class="arm-defined-word">RES0</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-7_4">ITS_Number, bits [7:4]</h4><div class="field"><p>In FEAT_GICv3 implementations this field is <span class="arm-defined-word">RES0</span>.</p>
<p>In FEAT_GICv4 implementations with more than one ITS instance, this field indicates the ITS number for use with <span class="xref">'VMOVP GICv4.0' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</span>.</p>
<p>When <a href="ext-gits_typer.html">GITS_TYPER</a>.VMOVP is 1, this field may be implemented as <span class="arm-defined-word">RES0</span>.</p>
<p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this field is programmable or RO.</p>
<p>If this field is programmable, changing this field when GITS_CTLR.Quiescent == 0 or GITS_CTLR.Enabled == 1 is <span class="arm-defined-word">UNPREDICTABLE</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-3_2">Bits [3:2]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-1_1">ImDe, bit [1]</h4><div class="field"><p>In GICv3 implementations, this bit is <span class="arm-defined-word">RES0</span>.</p>
<p>In GICv4 implementations, this bit is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-0_0">Enabled, bit [0]</h4><div class="field">
      <p>Controls whether the ITS is enabled:</p>
    <table class="valuetable"><tr><th>Enabled</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The ITS is not enabled. Writes to <a href="ext-gits_translater.html">GITS_TRANSLATER</a> are ignored and no further command queue entries are processed.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The ITS is enabled. Writes to <a href="ext-gits_translater.html">GITS_TRANSLATER</a> result in interrupt translations and the command queue is processed.</p>
        </td></tr></table><p>If a write to this register changes this field from 1 to 0, the ITS must ensure that both:</p>
<ul>
<li>Any caches containing mapping data are made consistent with external memory.
</li><li>GITS_CTLR.Quiescent == 0 until all caches are consistent with external memory.
</li></ul>
<p>Changing GITS_CTLR.Enabled from 0 to 1 when GITS_CTLR.Quiescent is 0 results in <span class="arm-defined-word">UNPREDICTABLE</span> behavior.</p><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h2>Accessing GITS_CTLR</h2><h4>GITS_CTLR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC ITS control</td><td><span class="hexnumber">0x0000</span></td><td>GITS_CTLR</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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